发明名称 PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP
摘要 Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.
申请公布号 US2010155957(A1) 申请公布日期 2010.06.24
申请号 US20070600901 申请日期 2007.12.17
申请人 SILICON WORKS CO., LTD. 发明人 HAN DAE-KEUN;KIM DAE-SEONG;NA JOON-HO
分类号 H01L23/485 主分类号 H01L23/485
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