发明名称 CIRCUIT VERIFICATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem wherein a fixed logic value cannot be propagated to a subsequent stage concerning a black box circuit block without logic information, while the number of processes and the processing time, which are required for verifying a circuit, are reduced by successively propagating the fixed logic value from a preceding stage circuit block to a subsequent stage circuit block since the fixed logic value is propagated to the subsequent stage when an output signal is expressed by a logical expression based on an input signal by each circuit block in circuit operation verification. Ž<P>SOLUTION: A circuit verification method propagates a fixed logic value even from a black box circuit block without logic information to a subsequent stage circuit by taking into consideration timing information. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010140104(A) 申请公布日期 2010.06.24
申请号 JP20080313641 申请日期 2008.12.09
申请人 RENESAS ELECTRONICS CORP 发明人 HATORI HIROKAZU
分类号 G06F17/50 主分类号 G06F17/50
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