发明名称 FAILURE DETECTION SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To provide a failure detection system for reliably detecting abnormal conditions while preventing the scale-up of an integrated circuit as much as possible. Ž<P>SOLUTION: By an inspecting object selection circuit 5, a plurality of transmission paths for severally transmitting respective failure detection signals are set either in a noneffective state in which the transmission of the detection signals is disabled or in an effective state in which the transmission of the detection signals is enabled. When the detection signals are transmitted to a transmission path set in an effective state, the detection signals are output to an interrupt controller 4. A CPU 2 switches a setting pattern related to the state setting of the effective and noneffective states of the respective transmission paths. Each time a setting pattern is switched, it is detected whether the detection signal is received from the inspecting object selection circuit 5 via the interrupt controller 4, thereby determining the source of the failure. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010139444(A) 申请公布日期 2010.06.24
申请号 JP20080317512 申请日期 2008.12.12
申请人 KYOCERA MITA CORP 发明人 OSADA YOSHIHIRO
分类号 G01R31/28 主分类号 G01R31/28
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