发明名称 |
Control circuit and method for a digital synchronous switching converter |
摘要 |
In addition to an output voltage control loop, a dead-time optimization loop is provided for a digital synchronous switching converter to dynamically adjust the dead-time for the power switches of the converter. It is extracted a minimal feedback signal at a steady state while the output voltage remains under a specification, and a maximal efficiency of the digital synchronous switching converter is thus obtained.
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申请公布号 |
US2010156376(A1) |
申请公布日期 |
2010.06.24 |
申请号 |
US20090654318 |
申请日期 |
2009.12.17 |
申请人 |
FU YI-CHIANG;CHANG WEI-HSU |
发明人 |
FU YI-CHIANG;CHANG WEI-HSU |
分类号 |
G05F1/00 |
主分类号 |
G05F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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