发明名称 Frequency Synchronization Using First and Second Frequency Error Estimators
摘要 An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.
申请公布号 US2010158183(A1) 申请公布日期 2010.06.24
申请号 US20080339333 申请日期 2008.12.19
申请人 发明人 HADZIC ILIJA;MORGAN DENNIS RAYMOND
分类号 H04L7/00 主分类号 H04L7/00
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