发明名称 PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR
摘要 A PLA contains an input plane (10) including a plurality of data lines (103) and a plurality of product term lines (104) having voltage levels changed in accordance with signal input to the plurality of data lines; and an output plane (20) including a plurality of product term lines (204) having voltage levels changed in accordance with the change of the voltage levels of the plurality of product term lines of the input plane and a plurality of data lines (203) for outputting signals in accordance with the voltage levels of the plurality of product term lines. In this PLA, at least one of the data lines of at least one of the input plane and the output plane has data terminals (101) at both ends thereof.
申请公布号 US2010156462(A1) 申请公布日期 2010.06.24
申请号 US20060997644 申请日期 2006.08.01
申请人 KATSURA AKIHITO 发明人 KATSURA AKIHITO
分类号 H03K19/177 主分类号 H03K19/177
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