发明名称 |
Delay locked loop circuit |
摘要 |
A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.
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申请公布号 |
US7741891(B2) |
申请公布日期 |
2010.06.22 |
申请号 |
US20080255056 |
申请日期 |
2008.10.21 |
申请人 |
HYNIX SEMICONDUCTOR, INC. |
发明人 |
KIM KYUNG-HOON |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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