| 摘要 |
A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for each reference clock signal group, and generating L main reference clock signals from the L×M sub reference clock signals; and sequentially delaying the L main reference clock signals, and generating the N multi-phase clock signals having the different phases. Because a plurality of clock signals having equal phase delay intervals between each other are generated regardless of the frequency of a received clock signal, the yield of Delay Locked Loop (DLL) circuits is improved using the multi-phase generating apparatus.
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