DOMAIN CROSSING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS

摘要

PURPOSE: A domain crossing circuit of a semiconductor memory apparatus is provided to implement a highly reliable operation in a high speed circuit by being synchronized with a clock edge. CONSTITUTION: A sampler(200) responds to a clock signal and delays an internal input signal by a certain interval, and it supplies a sampling internal signal and an edge information signal. An output stage responds to the edge information signal and synchronizes the internal signal with the clock signal to output a final output signal. A trigger signal generation block(220) samples the internal input signal at the falling edge and rising edge of the clock signal to supply a plurality of trigger signals. A combination block(240) selectively synchronizes the internal input signal at the falling edge and rising edge of the clock signal to supply a sampling internal signal. A clock edge information block(260) supplies the edge information of the clock which is an output reference of the sampling internal signal as edge information.