发明名称 SUBSTRATE FOR TESTING OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT TESTING SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To provide a substrate for testing of a semiconductor integrated circuit capable of drawing out wirings to external connection terminals, even if the number of electrodes of a wafer level CSP in a state of a wafer is huge, and to provide a semiconductor integrated circuit testing system using the same. Ž<P>SOLUTION: The substrate 1 for testing of the semiconductor integrated circuit is formed by laminating a lowest layer substrate 11, a second layer substrate 12, a third layer substrate 13, a top layer substrate 14, each of the substrates being a multilayer wiring board and having connectors 2 on a top surface of its outer periphery. The lowest layer substrate 11 includes lower surface terminals 111 connected to all electrodes 1100 of a wafer level CSP 1000 through pogo pins 2000. Internal wiring of the lowest layer substrate 11 connected to the lower surface terminals 111 is connected to the connectors 2 of one of the multilayer wiring boards. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010135635(A) 申请公布日期 2010.06.17
申请号 JP20080311274 申请日期 2008.12.05
申请人 TOSHIBA CORP 发明人 MIURA SHIGEKAZU
分类号 H01L21/66;G01R31/28 主分类号 H01L21/66
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