发明名称 PIPELINE TYPE A/D CONVERTER, HOLD CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a pipeline type A/D converter capable of operating with a high precision, without increase in power consumption. Ž<P>SOLUTION: The analog to digital converter is configured with a plurality of stages. The plurality of stages include: CAP 307a, 307b, 307c, 307d, SW 304c, 304d, 304a, 304k, 304l, and 304i for separately sampling analog differential input signals VPin and VNin; SW 304c, 304d, 304k, 304l for determining a sampling operation timing for a sampling circuit, multiple value output circuits 306, 309 for adjusting the value of the sampled signals VPin and VNin according to the value of a digital signal dj; an amplifier 305 for holding the adjusted signals VPin and VNin; SW 304b, 304j for transferring analog differential output signals VPout and VNout; and an SW 304q for short-circuiting and equalizing a terminal 310 and a terminal 311 prior to transfer. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010135905(A) 申请公布日期 2010.06.17
申请号 JP20080307522 申请日期 2008.12.02
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 NAKANISHI JUNYA
分类号 H03M1/14 主分类号 H03M1/14
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