SYSTEM AND METHOD FOR MAINTAINING CACHE COHERENCY ACROSS A SERIAL INTERFACE BUS

摘要

PURPOSE: A system and a method for maintaining cache coherency through a serial interface bus are provided to mark data received through a PCIe(Peripheral Component Interconnect express) bus as cacheable, thereby improving the speed of a processor. CONSTITUTION: The first processor generates a snoop request. A snoop request comprises destination information and a cache line address. The first processor transmits the snoop request to the second processor(118) through a serial interface bus(102). The first processor performs a processing operation by using the first data of a local memory. The second processor determines whether the second data of the cache line address is coherent with regards to the first data.