发明名称 |
SHARED CACHE MEMORIES FOR MULTI-CORE PROCESSORS |
摘要 |
Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.
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申请公布号 |
US2010153649(A1) |
申请公布日期 |
2010.06.17 |
申请号 |
US20080335381 |
申请日期 |
2008.12.15 |
申请人 |
LI WENLONG;CHEN YU;KIM CHANGKYU;HUGHES CHRISTOPHER J;CHEN YEN-KUANG |
发明人 |
LI WENLONG;CHEN YU;KIM CHANGKYU;HUGHES CHRISTOPHER J.;CHEN YEN-KUANG |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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