PLL HAVING BIAS GENERATOR TO REDUCE NOISE AND BIAS GENERATOR

摘要

PURPOSE: A phase locked loop and a bias generator thereof are provided to minimize the generation of a jitter of a phase locked loop by forming the noise characteristic of a bias generator and a regulator to be opposite. CONSTITUTION: A phase detection part(10) outputs an up signal and a down signal by comparing the phase of an input clock signal with the phase of an output clock signal. A charge pump(20) outputs a pumping voltage by charging and discharging an electric charge in response to the up signal and the down signal. A loop filter(30) outputs a filtering voltage by filtering the pumping voltage. A bias generator(40) generates a bias voltage which is inversely proportional to the power supply voltage. The bias voltage is applied to a regulator(50). The regulator outputs a control voltage which has same voltage level as the filtering voltage according to the filtering voltage. A voltage controlled oscillator(60) controls the frequency of the output clock signal in response to the control voltage.