| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital video processing circuit capable of suppressing the occurrence of horizontal jitter, having small circuit scale and low in power consumption. Ž<P>SOLUTION: A horizontal synchronization signal edge detection circuit 12 detects the edge timing of a horizontal synchronization signal included in an analog video signal Va before AD conversion from a digital video signal Vd after the AD conversion. An oversampling clock generation circuit 13 generates an oversampling clock CK1; and a frequency dividing circuit 14 generates a frequency dividing clock CK2. A clock changeover switch 16 selects the oversampling clock CK1 in periods before and after the edge timing, and selects the frequency dividing clock CK2 in the other periods. An AD conversion part 11 executes AD conversion in accordance with a sampling clock SCK selected by the clock changeover switch 16. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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