| 摘要 |
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function. |
