DIRECT DIGITAL SYNTHESIZER FOR REFERENCE FREQUENCY GENERATION

摘要

A direct digital frequency synthesizer having a mult i-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P(1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fOut that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.