发明名称 |
ENCRYPTION PROCESSING APPARATUS AND CALCULATION METHOD |
摘要 |
<p>Disclosed is an encryption processing apparatus in which the size of the circuitry of the calculation circuit that performs calculation including non-linear calculation is reduced and in which it is possible to adopt countermeasures against side-channel attacks. A SubBytes calculation section and InvSubBytes calculation section are integrated into a calculation section in which it is assumed that an affine conversion section (51) inputs data with a fixed mask (mfx1) and outputs converted data with a fixed mask (mfx2). XOR calculation sections (61), (62) replace the temporary data mask (m1) with the fixed mask (mfx1). The fixed mask (mfx1) is assumed to be invariant by the affine conversion section (51). As a result, replacement of the fixed mask (mfx1) after the affine conversion section (51) becomes unnecessary when decryption is carried out. It is assumed that the fixed mask (mfx2) that is affixed to the output data of an inverse calculation section (53) is also invariant by the affine conversion section (52). As a result, replacement of the fixed mask (mfx2) after the affine conversion section (52) becomes unnecessary when encryption is carried out.</p> |
申请公布号 |
WO2010067827(A1) |
申请公布日期 |
2010.06.17 |
申请号 |
WO2009JP70618 |
申请日期 |
2009.12.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA;FUJISAKI, KOICHI;SHIMBO, ATSUSHI |
发明人 |
FUJISAKI, KOICHI;SHIMBO, ATSUSHI |
分类号 |
G09C1/00;H04L9/28 |
主分类号 |
G09C1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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