| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a high frequency module reducing a phase control error. <P>SOLUTION: The high frequency module is provided with a high speed logic circuit for which high speed digital signals and a high speed clock are input signals and the phase of the clock relative to the digital signals is adjusted by a phase shifter so as to output signals without errors. The phase information of the digital signals and the clock is fed back to the phase shifter as phase control signals, through a phase locked loop including: a phase comparator for detecting a phase difference between the digital signals and the clock input from the phase shifter to the high speed logic circuit; and a synchronous detection circuit for extracting synchronous detection output on the basis of the phase difference signals of the phase comparator. <P>COPYRIGHT: (C)2010,JPO&INPIT |
