| 摘要 |
[Problems] To realize a log likelihood ratio calculation performed at a higher speed while the circuit size and the power consumption are reduced, regardless of the multilevel number of a modulation method. [Means for Solving the Problems] A hard-decision bit of the bits indicating the P-axial coordinate of a reception signal point is input to an area detection circuit, and based on the hard-decision bit input, the area detection circuit detects and outputs an area on the phase plane where the coordinate of the reception signal point is present. A soft-decision bit of the bits indicating the coordinate of the reception signal point is input to an LLR circuit, and based on the soft-decision bit input, the LLR circuit calculates a primary LLR. An LLR converter calculates the final LLR based on an output (area detection result) from the area detection circuit. With this configuration, a log likelihood ratio is calculated while limiting the scope, within which the value of the log likelihood ratio varies corresponding to the position of the reception signal point, to a range between adjacent signal points including the hard-decision threshold of the bit.
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