| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic verification apparatus for, when any indeterminate value is generated in logic verification, preventing the indeterminate value from being unintentionally erased. SOLUTION: A simulation part 63 performs a simulation based on the description of a logic function described in hardware description language. A second symbol replacing part 64 replaces an indeterminate value generated in the simulation by the simulation part 63 with a symbol. The simulation part 63 generates a symbol expression and propagates it to an element at a later stage when the symbol replaced by the second symbol replacing part 64 reaches an element being processed. Accordingly, unintentional erasing of the indeterminate value generated during the simulation can be prevented. COPYRIGHT: (C)2010,JPO&INPIT |
