| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device having two port memories enabling a higher speed, and a memory macro. <P>SOLUTION: The semiconductor device includes a memory circuit having one input port and one output port, a reading port, a writing port, and a memory timing control circuit. The memory timing control circuits generates each next timing signal. Having received an external clock signal, the memory timing control circuit generates a first timing signal necessary for a reading operation of the memory circuit by using a first delay circuit. Having received a reading operation end signal of the memory circuit based on the first timing signal, the memory timing control circuit generates a second timing signal for resetting the memory circuit. Having received the second timing signal, the memory timing control circuit generates a third timing signal necessary for a writing operation of the memory circuit by using a third delay circuit. For the external clock signal, a time difference between the rear edge of the third timing signal and the front edge of a next cycle is set larger than time necessary for resetting the memory circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
