| 摘要 |
<p>An apparatus and/or a method configuring a shared cache (246, 346, 446, 546, 646) to store input/output data for a processor (240, 340). The processor including a plurality of processor cores (242a, 242b, 242c, 342, 442, 542, 642). The apparatus and/or the method further storing the input/output data from and to an input/output device (232a, 232b, 234, 332a, 332b, 334, 432, 532, 632) on the shared cache and accessing the input/output data stored on the shared cache by at least one of the plurality of processor cores.</p> |
