发明名称 Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
摘要 A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux.
申请公布号 US7737726(B1) 申请公布日期 2010.06.15
申请号 US20080334186 申请日期 2008.12.12
申请人 RENSSELAER POLYTECHNIC INSTITUTE 发明人 ZHANG TONG;LI SHU
分类号 H01L25/00;H03K19/177 主分类号 H01L25/00
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