发明名称 Video signal processor and video signal processing method
摘要 According to one embodiment, a video signal processor has a moving block determining module, a vertical edge detector, a moving block number counter, a moving field determining module, a pulldown pattern detector, and a pulldown signal determining module. The moving block determining module divides each field configuring an input video signal into a plurality of blocks, and determines a motion of a block within the plurality of blocks, the block of which the motion is determined having a same spatial position within two fields adjacent to each other. The vertical edge detector detects a vertical edge within each of the plurality of blocks in the each field. The moving block number counter counts a number of moving blocks excluding a block having the vertical edge within a screen based on the detection result of the vertical edge detector and the determination result of the moving block determining module. The moving field determining module determines a motion between the each field based on the counting result of the moving block number counter. The pulldown pattern detector detects a 2:2 pulldown pattern based on the determination result of the moving field determining module. The pulldown signal determining module determines whether the input video signal is a 2:2 pulldown signal depending on the detection result of the pulldown pattern detector.
申请公布号 US7738041(B2) 申请公布日期 2010.06.15
申请号 US20080341821 申请日期 2008.12.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMAUCHI HIMIO
分类号 H04N5/46;H04N11/20 主分类号 H04N5/46
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