发明名称 |
Inspection plan optimization based on layout attributes and process variance |
摘要 |
Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.
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申请公布号 |
US7739065(B1) |
申请公布日期 |
2010.06.15 |
申请号 |
US20070761455 |
申请日期 |
2007.06.12 |
申请人 |
PDF SOLUTIONS, INCORPORATED |
发明人 |
LEE SHERRY F.;HARRIS KENNETH R.;JOSEPH DAVID |
分类号 |
G01N17/02 |
主分类号 |
G01N17/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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