TEST ENABLE SIGNAL GENERATION CIRCUIT AND SEMICON DUCTOR MEMORY DEVICE USING THE SAME

摘要

PURPOSE: A test enable signal generation circuit and a semiconductor memory device are provided to implement the test with same pattern regardless of a normal cell array and a redundancy cell array of a column redundancy domain by selecting the cell array tested according to the state of an input signal. CONSTITUTION: A first input pad(30) is inputted a first input signal. A second input pad(31) is inputted a second input signal. A buffer(32) generates a first and a second inner signal with buffering the first and the second input signal inputted from the first and the second input pad. An enable signal generator(33) is inputted the first and the second inner signal, and a first and a second test signal and a parallel test signal. The enable signal generator generates the first enable signal and the second enable signal. The first enable signal is enabled to test a redundancy cell array of a row redundancy domain.