发明名称 |
Phase-locked loop including sampling phase detector and charge pump with pulse width control |
摘要 |
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.
|
申请公布号 |
US7737743(B1) |
申请公布日期 |
2010.06.15 |
申请号 |
US20080044522 |
申请日期 |
2008.03.07 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
GAO XIANG;KLUMPERINK ERIC A. M.;NAUTA BRAM;BOHSALI MOUNIR;KIAEI ALI;SOCCI GERARD;DJABBARI ALI |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|