| 摘要 |
A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.
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