发明名称 Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System
摘要 An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.
申请公布号 US2010140750(A1) 申请公布日期 2010.06.10
申请号 US20080332302 申请日期 2008.12.10
申请人 QUALCOMM INCORPORATED 发明人 TOMS THOMAS R.
分类号 H01L21/98;H01L23/538 主分类号 H01L21/98
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