CLOCK GENERATING APPARATUS, AND JITTER REDUCING METHOD IN THE SAME

摘要

PROBLEM TO BE SOLVED: To generate a clock signal having less jitter.

SOLUTION: An apparatus includes a change rate correcting means having a DDS circuit for generating a cyclical signal and a comparator for outputting a binarized signal by comparing an input signal with a reference signal, and making correction for increasing a change rate at a cross point with the reference signal relating to the cyclical signal generated in the DDS circuit.

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