发明名称 STACKED DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF
摘要 A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in stacked memory devices because antimony can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices in a stacked memory device with well-controlled channel lengths may be achieved.
申请公布号 US2010140679(A1) 申请公布日期 2010.06.10
申请号 US20080329477 申请日期 2008.12.05
申请人 WALKER ANDREW J 发明人 WALKER ANDREW J.
分类号 H01L29/788 主分类号 H01L29/788
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