发明名称 PATTERN FORMING METHOD AND PATTERN VERIFICATION PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To improve resist dimension accuracy and to improve a yield in the production of a semiconductor device. <P>SOLUTION: A first pattern and a second pattern different from each other are extracted from a first mask pattern created on the basis of a first design pattern; a best focus difference between the first pattern and the second pattern is calculated on the basis of first exposure conditions; the best focus difference is compared with a predetermined threshold; and when the best focus difference is larger than the threshold, the first design pattern is corrected to create a second design pattern. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010128279(A) 申请公布日期 2010.06.10
申请号 JP20080304132 申请日期 2008.11.28
申请人 TOSHIBA CORP 发明人 FUKUHARA KAZUYA
分类号 G03F1/36;G03F1/68;G03F1/70;H01L21/027 主分类号 G03F1/36
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