发明名称 METHOD OF MANUFACTURING MULTI-LEVEL CONTACTS BY SIZING OF CONTACT SIZES IN INTEGRATED CIRCUITS
摘要 A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.
申请公布号 KR100962312(B1) 申请公布日期 2010.06.10
申请号 KR20057001937 申请日期 2003.07.09
申请人 发明人
分类号 H01L21/28;H01L21/768 主分类号 H01L21/28
代理机构 代理人
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