发明名称 Method of improving noise characteristics of an ADPLL and a relative ADPLL
摘要 A method of improving noise characteristics of an all-digital phase locked loop generating a feedback word representing a continuous-time oscillating signal, including a time-to-digital converter input with the continuous-time oscillating signal and a reference signal function of a reference clock, the time-to-digital converter generating a digital word representing either the ratio between the oscillating signal and the reference signal or the DCO output phase, the feedback word being a function of said digital word, comprises the step of corrupting with a dither signal at least one among the reference clock, the digital word and the oscillating signal. This method is implemented by a respective feedback circuit for an all-digital phase locked loop.
申请公布号 EP2194646(A1) 申请公布日期 2010.06.09
申请号 EP20090177501 申请日期 2009.11.30
申请人 发明人
分类号 H03L7/099 主分类号 H03L7/099
代理机构 代理人
主权项
地址