发明名称 System and method enabling circuit topology recognition with auto-interactive constraint application and smart checking
摘要 A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-circuit; modifying the match expression to change the matching properties of components of the sub-circuit; and producing an information structure in a computer readable medium, where the information structure associates a graph representing a topology of the selected sub-circuit with the modified match expression. Subsequently, the information structure corresponding to the selected sub-circuit can be identified in a given circuit design.
申请公布号 US7735036(B2) 申请公布日期 2010.06.08
申请号 US20070745983 申请日期 2007.05.08
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 DENNISON IAN CAMPBELL;BAKER MARK;ARSINTESCU BOGDAN;O'RIORDAN DONALD JOHN
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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