| 摘要 |
A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.
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