发明名称 Enhanced processor element structure in a reconfigurable integrated circuit device
摘要 A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.
申请公布号 US7734896(B2) 申请公布日期 2010.06.08
申请号 US20060390131 申请日期 2006.03.28
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 FURUKAWA HIROSHI
分类号 G06F15/76 主分类号 G06F15/76
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