| 摘要 |
A receiver includes, in series, at least one receive antenna, a buffer, and arithmetic logic block, a symbol detector, and a phase noise estimator. A further feedback loop couples an output of the phase noise estimator to an input of the arithmetic logic block for providing an estimate of phase noise. The buffer is for storing the received signal. The arithmetic logic block, such as a multiplier, is for removing the estimate of phase noise, received via the feedback loop, from the buffered signal. The symbol detector is for estimating a symbol from the output of the arithmetic logic block. The phase noise estimator estimates phase noise from two inputs received from the symbol detector: the estimated symbol and the remainder signal. Preferably, the phase noise estimator performs an IFFT on these two inputs and Kalman filters the result. Iteratively estimating the phase noise improves precision substantially. |
