发明名称 Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method
摘要 A validation/correction method is provided for design data or mask data by which a pattern which becomes critical in a process is extracted in advance so that the pattern can be corrected. Consequently, the process spec is achieved in a short period of time after OPC or process proximity effect correction (PPC).
申请公布号 US7735053(B2) 申请公布日期 2010.06.08
申请号 US20070819397 申请日期 2007.06.27
申请人 SHARP KABUSHIKI KAISHA 发明人 HARAZAKI KATSUHIKO
分类号 G06F17/50;G03F1/36;G03F1/68;G03F1/70 主分类号 G06F17/50
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