METHOD AND APPARATUS FOR IMPROVING SPEED OF PULSED LATCH-BASED DIGITAL SEQUENTIAL CIRCUITS

摘要

PURPOSE: A method and an apparatus for improving the speed of pulsed latch-based digital sequential circuits are provided to effectively reduce a clock period in a digital sequential circuit using simultaneously various pulse widths and clock skew scheduling. CONSTITUTION: A net list of a gate level is input. Corresponding pulse width and clock skew are allocated in a plurality of latches which is included in the sequential circuit(S110). The latches are grouped to form a latch group. The latch group is allocated in a pulse generator(S120). A circuit arrangement process and a routing process are performed(S130). A clock tree is synthesized in order to form a clock skew(S140).