| 摘要 |
According to one embodiment, an extreme data rate DRAM is a DRAM resetting data thereof in response to a reset signal. When power is initially supplied to a system, a system controller outputs the reset signal to the extreme data rate DRAM in response to a reset signal input from a memory controller through a level shifter. When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.
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