| 摘要 |
A data-processing unit comprises a register unit (10) comprising a register (20, R0-R3). The data-processing unit further comprises an address-generation unit (30) for generating a memory address to a memory unit (60). The address-generation unit (30) is adapted to fetch, from the register (20, R0-R3), a base address stored in a first portion (20a) of the register (20, R0-R3) and a first offset address stored in a second portion (20b) of the register (20, R0-R3). The base address and the first offset address are represented with fewer bits than the memory address. The address generation unit (30) is adapted to receive a first instruction and, in response thereto, generate a second offset address based on the first offset address, and generate the memory address by adding the base address and the second offset address. A method for generating the memory address is also disclosed.
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