| 摘要 |
PURPOSE: A variable-gain amplifying method and system are provided to suppress the distortion of a variable-gain amplifier(VGA) circuit by floating the AC gate voltage of an n-channel MOS(NMOS) tap transistor with an average source/drain voltage. CONSTITUTION: An attenuator ladder(170) comprises a plurality of attenuator nodes which are serially connected. Each attenuator node uses the NMOS tap transistor Q1(130-a), Q2(130-b), Q3(130-c), Q4(130-d) and Q5(130-e) and RC networks(120-a, 120-b, 120-c, 120-d, 120-e). The different attenuator node is serially connected to the source terminal of the tap transistor through resistance sets(180-a, 180-b, 180-c, 180-d). The different attenuator node is coupled with the output(155) of the VGA(100). The source of the tap transistor is individually connected to the ground through a corresponding resistance. The drains of every tap transistors are coupled with the input(150) of an amplifier(160) which generates the output(190) of the VGA. |
