发明名称 DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a data processor for changing arithmetic granularity. SOLUTION: An OR circuit 34 selects, based on the arithmetic granularity, a carry to be generated by the operation of a low-order bit to be outputted from an arithmetic circuit 32 in a PE(2n)21-1 or a carry to be generated by the operation of a high-order bit to be outputted from the arithmetic circuit 32 in a PE(2n+1)21-2, and then, outputs the selection result to the arithmetic circuit 32 in the PE(2n)21-1. An OR circuit 37 selects, based on the arithmetic granularity, a carry to be generated by the operation of a high-order bit to be outputted from the arithmetic circuit 32 in the PE(2n+1)21-2 or a carry to be generated by the operation of the low-order bit to be outputted from the arithmetic circuit 32 in the PE(2n)21-1, and outputs the selection result to the arithmetic circuit 32 in the PE(2n+1)21-2. Consequently, the arithmetic granularity is changeable. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010122741(A) 申请公布日期 2010.06.03
申请号 JP20080293510 申请日期 2008.11.17
申请人 KUMAMOTO UNIV;RENESAS TECHNOLOGY CORP 发明人 SUEYOSHI TOSHINORI;IIDA MASAHIRO;MIZOGAMI YUTA;NAKANO MITSUOMI;MIZUMOTO KATSUYA
分类号 G06F9/38 主分类号 G06F9/38
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