EIGHT-TRANSISTOR LOW LEAKAGE SRAM CELL

摘要

<P>PROBLEM TO BE SOLVED: To provide an SRAM cell for obtaining a stable operation regardless of a low operating voltage and a large number of cell arrays. Ž<P>SOLUTION: A static random access memory (SRAM) cell is disclosed. The SRAM includes: a pair of cross-coupled inverters having a first storage node; and an N-type MOS transistor having a gate electrode and first and second source/drain electrodes individually connected to the first storage node and mutually connected to a read word-line (RWL) and a first read bit-line (RBL) where the RWL and first RBL are activated during a read operation but not activated during a write operation. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž