| 摘要 |
<P>PROBLEM TO BE SOLVED: To maintain the high speed of selecting circuit operation regardless of the increase of a frequency division ratio. Ž<P>SOLUTION: A fixed value of a fixed period according to a frequency division ratio is output from a decoder 3 to respective preceding stages of D flip flops in a plurality of stages of a shift register 2, and an output signal from the decoder 3 and output signals from D flip flops in preceding stages are switched to the output signal from the decoder 3 by selectors 40 to 48 when a load signal LOAD from a D flip flop SETCNT0 in the last stage is in a high level. When an output signal from the D flip flop SETCNT0 in the last stage out of D flip flops SETCNT0 to 8 in the plurality of stages is in a high level, a Q output from the D flip flop SETCNT0 in the last stage is inverted and output from a toggle flip flop 5 as a frequency division signal DIVOUT. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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