| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit which includes a PHY circuit connected to a link transmission path complying with an PCI Express and greatly reduces power consumption in comparison with the conventional technology in an L1 state. <P>SOLUTION: A clock controller 53 outputs a reference clock signal REFCLK from a reference clock signal generation circuit 3 to the PHY circuit 52 in an L0 state, and meanwhile, controls a switch SW to output a clock signal CL2 from a generation circuit 54 to the PHY circuit 52 in the L1 state and stops the operation of the reference clock signal generation circuit 3. In addition, a link controller 51 stops the operation of a PLL circuit 55 in the L1 state. The PHY circuit 52 uses the clock signal CL2 to detect a data packet from a root complex device 2 in the L1 state. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
