| 摘要 |
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge triggered latches clocked by said input clock signal (CLKin), wherein a last edge triggered latch of said serially connected edge triggered latches (4) inverts a triggering direction of a first edge triggered latch (4A) of said serially connected edge triggered latches (4).
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