发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a redundant relieving circuit of a memory for shortening a test time of the memory. SOLUTION: The circuit is provided with a plurality of memories 10a to 10n which can store data, a built-in self-test circuit 20 performing tests of a plurality of memories, and an analyzing circuit 30 analyzing a test result of the built-in self-test circuit. The built-in self-test circuit is provided with a test control part 21 generating a memory selecting signal, an address generating part 23 generating a write-in address, a data generating part 22 generating an output expected value, and a control signal generating part 24 generating a control signal. The analyzing circuit is provided with a memory output selecting part 31 switching output data of a plurality of memories based on the memory selecting signal, a bit comparing part 34 comparing the output data with the output expected value for each bit, a normal/defective condition discriminating part 36 performing normal/defective condition discrimination of a memory, a normal/defective condition discriminating register 38, a relieving analyzing part 35 generating relieving solution, a plurality of relieving solution registers 37 provided corresponding to a plurality of memories respectively and storing relieving solution, and an output part 39. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010123159(A) 申请公布日期 2010.06.03
申请号 JP20080293457 申请日期 2008.11.17
申请人 TOSHIBA CORP 发明人 YASUKURA KENICHI;TOKUNAGA CHIKAKO
分类号 G11C29/12;G11C29/44 主分类号 G11C29/12
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